A factorization method for FPGA implementation of Sample Rate Converter for a multi-standard radio communications

In modern radio communications systems Digital Down Converters (DDC) play a significant role to receive a transmitted signal. The transmitted signal, which is usually a bandpass signal riding over a high intermediate frequency gets sampled at a very higher rate than the ideal Nyquist rate due to the phenomenon of bandpass sampling. Hence a Digital Down converter is used to lower the sampling rate, which eliminates the need of a high speed digital signal processing and reduces power consumption. In this paper we present an architectural implementation of DDC suitable for multi- standard radio communication systems. We have implemented a DDC on FPGA suiting various wireless standards viz, WiMAX 802.16, WCDMA, CDMA2000 and GSM system by the method of factorization [1]. The implemented architecture uses CORDIC algorithm as a mixer in the IF stage and a Cascaded Integrated Comb filter as a decimation filter. We have compared the hardware resources utilized for this multi- standard DDC with a radio communication system with a single standard. The hardware resources for a multi- standard radio have increased by less than fifteen percent.