Impedance Design for Multi-layered Vias

被引：0
作者：
Gu, Xiaoxiong [1 ]
Ruehli, Albert E. [1 ]
Ritter, Mark B. [1 ]
机构：
[1] IBM TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA
来源：
2008 IEEE-EPEP ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING | 2008年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a methodology based on a semi-analytical scattering model to pre-design the characteristic impedance of multi-layered through hole vias by choosing appropriate via geometrical parameters, dielectric property, and the placement of ground vias. A linear model as a function of design parameters above is further applied to analyze the statistical variation of impedance for different tolerance specification.
引用
收藏
页码：297 / 300
页数：4
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