Equivalence Checking for Intelligent Circuits

被引：0
|
作者：
Fan, De-Hui [1 ]
Ma, Guang-Sheng [1 ]
机构：
[1] Harbin Engn Univ, Coll Comp Sci & Technol, Harbin, Peoples R China
来源：
2008 INTERNATIONAL SYMPOSIUM ON INTELLIGENT INFORMATION TECHNOLOGY APPLICATION WORKSHOP: IITA 2008 WORKSHOPS, PROCEEDINGS | 2008年
关键词：
formal verification; equivalence checking; WGL;
D O I：
10.1109/IITA.Workshops.2008.188
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Equivalence checking is playing a significant role in Intelligent Circuits design. However, the common models for verification either have their complexity problems or have applicable limitations. In order to overcome the deficiencies, a model WGL (Weighted Generalized List) is proposed and based on WGL we give an algorithm for cheking. comparing the model WLDDs, the experiments show that the WGL is more efficient.
引用
收藏
页码：785 / 787
页数：3
相关论文
共 50 条
  • [41] Exploiting Inherent Characteristics of Reversible Circuits for Faster Combinational Equivalence Checking
    Amaru, Luca
    Gaillardon, Pierre-Emmanuel
    Wille, Robert
    De Micheli, Giovanni
    PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 175 - 180
  • [42] Equivalence Checking of Nonlinear Analog Circuits for Hierarchical AMS System Verification
    Steinhorst, Sebastian
    Hedrich, Lars
    2012 IEEE/IFIP 20TH INTERNATIONAL CONFERENCE ON VLSI AND SYSTEM-ON-CHIP (VLSI-SOC), 2012, : 135 - 140
  • [43] Equivalence checking of quantum circuits by nonlocality (vol 8, 139, 2022)
    Sun, Weixiao
    Wei, Zhaohui
    NPJ QUANTUM INFORMATION, 2022, 8 (01)
  • [44] Equivalence Checking Methods for Analog Circuits Using Continuous Reachable Sets
    Tarraf, Ahmad
    Hedrich, Lars
    Kochdumper, Niklas
    Rechmal-Lesse, Malgorzata
    Olbrich, Markus
    2020 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI 2020), 2020, : 7 - 12
  • [45] Equivalence Checking of Parameterized Quantum Circuits Verifying the Compilation of Variational Quantum Algorithms
    Peham, Tom
    Burgholzer, Lukas
    Wille, Robert
    2023 28TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC, 2023, : 702 - 708
  • [46] Using Range-equivalent Circuits for Facilitating Bounded Sequential Equivalence Checking
    Chen, Yung-Chih
    Ji, Wei-An
    Wang, Chih-Chung
    Huang, Ching-Yi
    Wu, Chia-Cheng
    Lin, Chia-Chun
    Wang, Chun-Yao
    2018 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), 2018,
  • [47] A compositional approach for equivalence checking of sequential circuits with unknown reset state and overlapping partitions
    Bischoff, Gabriel P.
    Brace, Karl S.
    Cabodi, Gianpiero
    COMPUTER AIDED SYSTEMS THEORY- EUROCAST 2007, 2007, 4739 : 505 - +
  • [48] Checking the circuits
    Forbes, M.
    ELECTRONICS WORLD, 2008, 114 (1866): : 38 - 38
  • [49] Sequential equivalence checking
    Mathur, A
    Fujita, M
    Balakrishnan, M
    Mitra, R
    19TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS, 2005, : 18 - 19
  • [50] Partially redundant logic detection using symbolic equivalence checking in reversible and irreversible logic circuits
    Feinstein, David Y.
    Thornton, Mitchell A.
    Miller, D. Michael
    2008 DESIGN, AUTOMATION AND TEST IN EUROPE, VOLS 1-3, 2008, : 1490 - +
12345