Equivalence Checking for Intelligent Circuits

被引：0
|
作者：
Fan, De-Hui [1 ]
Ma, Guang-Sheng [1 ]
机构：
[1] Harbin Engn Univ, Coll Comp Sci & Technol, Harbin, Peoples R China
来源：
2008 INTERNATIONAL SYMPOSIUM ON INTELLIGENT INFORMATION TECHNOLOGY APPLICATION WORKSHOP: IITA 2008 WORKSHOPS, PROCEEDINGS | 2008年
关键词：
formal verification; equivalence checking; WGL;
D O I：
10.1109/IITA.Workshops.2008.188
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
Equivalence checking is playing a significant role in Intelligent Circuits design. However, the common models for verification either have their complexity problems or have applicable limitations. In order to overcome the deficiencies, a model WGL (Weighted Generalized List) is proposed and based on WGL we give an algorithm for cheking. comparing the model WLDDs, the experiments show that the WGL is more efficient.
引用
收藏
页码：785 / 787
页数：3
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