Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing

被引：7
|
作者：
Lopich, Alexey [1 ]
Dudek, Piotr [1 ]
机构：
[1] Univ Manchester, Sch Elect & Elect Engn, Manchester M60 1QD, Lancs, England
来源：
JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY | 2009年 / 56卷 / 01期
基金：
英国工程与自然科学研究理事会;
关键词：
Binary skeletonization; Asynchronous processing; Wave propagations; Grassfire transformation; THINNING ALGORITHM; DIGITAL PICTURES; VISION CHIP; DESIGN; ARRAY; METHODOLOGIES; PROPAGATION; REALIZATION; CIRCUITS; ELEMENTS;
D O I：
10.1007/s11265-008-0283-6
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an FPGA realisation of an application-specific cellular processor array designed for asynchronous skeletonization of binary images. The skeletonization algorithm is based on iterative thinning utilizing a 'grassfire' transformation approach. The purpose of this work was to test the performance of a fully parallel asynchronous processor array and to evaluate the inhomogeneity of wave propagation velocity. A proof-of-concept design has been implemented and evaluated, the results are presented and discussed.
引用
收藏
页码：91 / 103
页数：13
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