Design of CMOS three-stage amplifiers for near-to-minimum settling-time

被引：8
作者：
Giustolisi, Gianluca [1 ]
Palumbo, Gaetano [1 ]
机构：
[1] Univ Catania, Dipartimento Ingn Elettr Elettron & Informat, Viale A Doria 6, I-95125 Catania, Italy
来源：
MICROELECTRONICS JOURNAL | 2021年 / 107卷
关键词：
Settling-time; Operational transconductance amplifiers; Three-stage amplifiers; Feedback amplifiers; CMOS; Low-voltage; COMPENSATION STRATEGY; OPTIMIZATION;
D O I：
10.1016/j.mejo.2020.104939
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
In this paper, we provide a new procedure that allows to design a generic three-stage amplifier from settling-time specifications. The procedure analyze the settling-time of pure twoor three-pole amplifiers (i.e., with no zeros) and extends the results to a generic amplifier that includes one or two zeros even placed in the right-half plane. The validity of the proposed approach is demonstrated through a design example of a three-stage CMOS amplifier suitable for switched-capacitor applications.
引用
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页数：10
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