Prefetch injection based on hardware monitoring and object metadata

被引:14
|
作者
Adl-Tabatabai, AR [1 ]
Hudson, RL [1 ]
Serrano, MJ [1 ]
Subramoney, S [1 ]
机构
[1] Intel Corp, Microprocessor Technol Lab, Programming Syst Lab, Santa Clara, CA USA
关键词
prefetching; compiler optimization; garbage collection; cache misses; profile-guided optimization; virtual machines;
D O I
10.1145/996893.996873
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
Cache miss stalls hurt performance because of the large gap between memory and processor speeds - for example, the popular server benchmark SPEC JBB2000 spends 45% of its cycles stalled waiting for memory requests on the Itanium(R) 2 processor. Traversing linked data structures causes a large portion of these stalls. Prefetching for linked data structures remains a major challenge because serial data dependencies between elements in a linked data structure preclude the timely materialization of prefetch addresses. This paper presents Mississippi Delta (MS Delta), a novel technique for prefetching linked data structures that closely integrates the hardware performance monitor (HPM), the garbage collector's global view of heap and object layout, the type-level metadata inherent in type-safe programs, and JIT compiler analysis. The garbage collector uses the HPM's data cache miss information to identify cache miss intensive traversal paths through linked data structures, and then discovers regular distances (deltas) between these linked objects. JIT compiler analysis injects prefetch instructions using deltas to materialize prefetch addresses. We have implemented MS Delta in a fully dynamic profile-guided optimization system: the StarJIT dynamic compiler [1] and the ORP Java virtual machine [9]. We demonstrate a 28-29% reduction in stall cycles attributable to the high-latency cache misses targeted by MS Delta and a speedup of 11-14% on the cache miss intensive SPEC JBB2000 benchmark.
引用
收藏
页码:267 / 276
页数:10
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