High-performance low-power bit-level systolic array signal processor with low-threshold dynamic logic circuits

被引:2
|
作者
Song, WS [1 ]
Vai, NM [1 ]
Nguyen, HT [1 ]
机构
[1] MIT, Lincoln Lab, Cambridge, MA 02139 USA
来源
CONFERENCE RECORD OF THE THIRTY-FIFTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS AND COMPUTERS, VOLS 1 AND 2 | 2001年
关键词
D O I
10.1109/ACSSC.2001.986895
中图分类号
TP31 [计算机软件];
学科分类号
081202 ; 0835 ;
摘要
MIT Lincoln Laboratory has developed a scalable full-custom cell library for implementing bit-level systolic array signal processors. The cell library achieves high performance and low power consumption by using dynamic logic circuits with low-threshold voltage CMOS devices. The cell library is designed to implement signal processing functions such as finite impulse response (FIR) filter, infinite impulse response (IIR)filter, polyphase filter bank, fast Fourier transform (FFT), inverse fast Fourier transform (IFFT), and matrix operations such as partial product computation and QR decomposition. The full custom cell library is highly optimized for fast clock speed, small area, and low power consumption. The low-threshold-voltage dynamic logic devices allow operation at high clock speeds with significantly reduced power supply voltage. The dynamic logic also greatly reduces the device count. The cell library is designed to scale to smaller fabrication geometry. Design automation is also possible by using customized placement and routing software. A FIR filter test chip has been designed, fabricated, and tested on a 0.25 micron 2.5 volt bulk CMOS process. The clock frequency exceeds 800 MHz running on only 1.3 volt power supply, and power efficiency up to 250 billion operations per second per watt has been demonstrated using power supply voltage down to 0.4 volt.
引用
收藏
页码:144 / 147
页数:4
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