How Affine Arithmetic Helps Beat Uncertainties in Electrical Systems

被引:21
作者
Ding, Tongyu [1 ]
Trinchero, Riccardo [2 ]
Manfredi, Paolo [3 ]
Stievano, Igor S. [2 ]
Canavero, Flavio G. [3 ]
机构
[1] Harbin Inst Technol, Harbin, Peoples R China
[2] Politecn Torino, Elect & Commun Engn, Turin, Italy
[3] Politecn Torino, Elect Engn, Turin, Italy
关键词
TOLERANCE ANALYSIS; POLYNOMIAL CHAOS; INTERVAL; INTERCONNECT;
D O I
10.1109/MCAS.2015.2484198
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The ever-increasing impact of uncertainties in electronic circuits and systems is requiring the development of robust design tools capable of taking this inherent variability into account. Due to the computational inefficiency of repeated design trials, there has been a growing demand for smart simulation tools that can inherently and effectively capture the results of parameter variations on the system responses. To improve product performance, improve yield and reduce design cost, it is particularly relevant for the designer to be able to estimate worst-case responses. Within this framework, the article addresses the worst-case simulation of lumped and distributed electrical circuits. The application of interval-based methods, like interval analysis, Taylor models and affine arithmetic, is discussed and compared. The article reviews in particular the application of the affine arithmetic to complex algebra and fundamental matrix operations for the numerical frequency-domain simulation. A comprehensive and unambiguous discussion appears in fact to be missing in the available literature. The affine arithmetic turns out to be accurate and more efficient than traditional solutions based on Monte Carlo analysis. A selection of relevant examples, ranging from linear lumped circuits to distributed transmission-line structures, is used to illustrate this technique.
引用
收藏
页码:70 / 79
页数:10
相关论文
共 27 条
[1]   Direct Computation of Statistical Variations in Electromagnetic Problems [J].
Ajayi, Ajibola ;
Ingrey, Philip ;
Sewell, Phillip ;
Christopoulos, Christos .
IEEE TRANSACTIONS ON ELECTROMAGNETIC COMPATIBILITY, 2008, 50 (02) :325-332
[2]  
[Anonymous], P 21 EUR SIGN PROC C
[3]  
[Anonymous], 2004, MATH ANAL
[4]  
[Anonymous], MONOGRAPH BRAZILIAN
[5]  
[Anonymous], P POW TECH C BOL IT
[6]  
Beetner D. G., 2007, PROC IEEE INT S ELEC, P1
[7]  
Berz M., 1998, Reliable Computing, V4, P83, DOI 10.1023/A:1009958918582
[8]   True worst-case circuit tolerance analysis using genetic algorithms and affine arithmetic [J].
Femia, Nicola, 2000, IEEE, Piscataway, NJ, United States (47)
[9]   Genetic optimization of interval arithmetic-based worst case circuit tolerance analysis [J].
Femia, N ;
Spagnuolo, G .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 1999, 46 (12) :1441-1456
[10]  
HO CW, 1975, IEEE T CIRCUITS SYST, VCA22, P504, DOI 10.1109/TCS.1975.1084079