共 50 条
- [1] Parameter synthesis for Piecewise Affine systems from temporal logic specifications HYBRID SYSTEMS: COMPUTATION AND CONTROL, 2008, 4981 : 542 - 555
- [2] Switching Protocol Synthesis for Temporal Logic Specifications 2012 AMERICAN CONTROL CONFERENCE (ACC), 2012, : 727 - 734
- [3] Parameter Synthesis for Signal Temporal Logic ELECTRONIC PROCEEDINGS IN THEORETICAL COMPUTER SCIENCE, 2014, (145): : 3 - +
- [5] SYNTHESIS OF COMMUNICATING PROCESSES FROM TEMPORAL LOGIC SPECIFICATIONS ACM TRANSACTIONS ON PROGRAMMING LANGUAGES AND SYSTEMS, 1984, 6 (01): : 68 - 93
- [6] Reactive Planner Synthesis Under Temporal Logic Specifications IEEE ACCESS, 2024, 12 : 13260 - 13276
- [8] Temporal Relaxation of Signal Temporal Logic Specifications for Resilient Control Synthesis 2022 IEEE 61ST CONFERENCE ON DECISION AND CONTROL (CDC), 2022, : 2890 - 2896
- [9] Robustness of temporal logic specifications FORMAL APPROACHES TO SOFTWARE TESTING AND RUNTIME VERIFICATION, 2006, 4262 : 178 - +
- [10] Automatic Synthesis of Human Motion from Temporal Logic Specifications 2020 IEEE/RSJ INTERNATIONAL CONFERENCE ON INTELLIGENT ROBOTS AND SYSTEMS (IROS), 2020, : 4040 - 4046