Effects of tolerances on sidelobe levels in slotted waveguide arrays

被引：0

作者：

Jahagirdar, DR ^{[1
]}

机构：

[1] Res Ctr Imarat, DRDO, Hyderabad 500069, Andhra Pradesh, India

来源：

IEEE ANTENNAS AND PROPAGATION SOCIETY SYMPOSIUM, VOLS 1-4 2004, DIGEST | 2004年

关键词：

D O I：

10.1109/APS.2004.1332079

中图分类号：

TN [电子技术、通信技术];

学科分类号：

0809 ;

摘要：

Fabrication tolerances are known to affect the electrical performance of slotted waveguide arrays. The effects on sidelobe level, pointing angle and gain is studied by introducing systematic and random errors in slot offsets, slot lengths and waveguide dimensions in the radiating layer of the array. Similar study was done by introducing errors in slot inclination angle, slot lengths and waveguide dimension in coupling layer. The study was also extended for analyzing the patterns away from resonance. The analysis helps to quantify the tolerance requirements on the critical dimensions of the slotted waveguide arrays. The results of analysis for Ku-band and Ka-band designs are presented as examples to support our conclusion.

引用

页码：3277 / 3280

页数：4