The IBM eServer z990 microprocessor

被引：27
作者：
Slegel, TJ
Pfeffer, E
Magee, JA
机构：
[1] IBM Syst & Technol Grp, Poughkeepsie, NY 12601 USA
[2] IBM Deutschland Entwicklung GmbH, IBM Syst & Technol Grp, D-71032 Boblingen, Germany
来源：
IBM JOURNAL OF RESEARCH AND DEVELOPMENT | 2004年 / 48卷 / 3-4期
关键词：
D O I：
10.1147/rd.483.0295
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The IBM eServer(TM) z990 microprocessor implements many features designed to give excellent performance on both newer and traditional mainframe applications. These features include a new superscalar instruction execution pipeline, high-bandwidth caches, a huge secondary translation-lookaside buffer (TLB), and an onboard cryptographic coprocessor. The microprocessor maintains zSeries(R) leadership in RAS (reliability, availability, serviceability) capabilities that include state-of-the-art error detection and recovery.
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收藏
页码：295 / 309
页数：15
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