A 360μW Vernier Time-to-Digital Converter for ADPLL in IoT Applications

被引：0

作者：

Xu, Yongxin ^{[1
]}

Yan, Na ^{[1
]}

Ma, Lei ^{[1
]}

Min, Hao ^{[1
]}

机构：

[1] Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China

来源：

PROCEEDINGS OF 2018 IEEE INTERNATIONAL CONFERENCE ON INTEGRATED CIRCUITS, TECHNOLOGIES AND APPLICATIONS (ICTA 2018) | 2018年

基金：

中国国家自然科学基金;

关键词：

overflow bits; Vernier time-to-digital converter; low power;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An improved Vernier time-to-digital converter (TDC) with overflow bits is designed for low power applications. The overflow hits are added to the Vernier-TDC to reduce the stages of the TDC, thus saving power. A digital-to-time convertor is employed to realize the fractional division and reduce the stages of TDC. Fabricated in 55-nm CMOS, TDC together with DTC consumes only 360 mu W when operating at 24 MHz. With the help of the TDC, the ADPLL achieves 1.69-ps(rms) jitter with a 24-MHz reference clock and a 1.8GHz output RF clock.

引用

页码：28 / 29

页数：2

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