Metal Floating Gate Memory Device With SiO2/HfO2 Dual-Layer as Engineered Tunneling Barrier

被引：16

作者：

Chen, Guoxing ^{[1
]}

Huo, Zongliang ^{[1
]}

Jin, Lei ^{[1
]}

Han, Yulong ^{[1
]}

Li, Xinkai ^{[1
]}

Liu, Su ^{[2
]}

Liu, Ming ^{[1
]}

机构：

[1] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

[2] Lanzhou Univ, Sch Phys Sci & Technol, Lanzhou 730000, Peoples R China

来源：

IEEE ELECTRON DEVICE LETTERS | 2014年 / 35卷 / 07期

基金：

中国国家自然科学基金;

关键词：

Metal floating gate memory; engineered tunneling barrier;

D O I：

10.1109/LED.2014.2320971

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Metal as floating gate (FG) in combination with high-k dielectrics has been seen as a possible solution to continue the scaling of NAND flash technology node beyond 2x nm. In this letter, it is demonstrated that stacked metal FG memory cell with SiO2/HfO2 dual-layer engineered tunneling barrier shows good memory characteristics. It presents favorable performance with lower operation voltage as well as enhanced program/erase speed. Furthermore, improvement of data retention is also obtained, proving that SiO2/HfO2 engineered tunnel barrier is promising for the improvement of metal FG memory performance.

引用

页码：744 / 746

页数：3

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