In-Memory Associative Processors: Tutorial, Potential, and Challenges

被引:7
作者
Fouda, Mohammed E. [1 ,2 ]
Yantir, Hasan Erdem [3 ]
Eltawil, Ahmed M. [4 ]
Kurdahi, Fadi [1 ]
机构
[1] Univ Calif Irvine, Ctr Embedded & Cyber Phys Syst, Irvine, CA 92697 USA
[2] Nile Univ, Nanoelect Integrated Syst Ctr, Giza 16453, Egypt
[3] TUBITAK Informat & Informat Secur Res Ctr, TR-41470 Kocaeli, Turkey
[4] King Abdullah Univ Sci & Technol, Elect & Comp Engn Dept, Thuwal 23955, Saudi Arabia
关键词
Program processors; Computer architecture; Table lookup; Transistors; Switches; Performance evaluation; Associative memory; Associative processor; in-memory computing; content-addressable memory; accelerators; SIMD; vector processor; ARCHITECTURES; INFERENCE;
D O I
10.1109/TCSII.2022.3170468
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In-memory computing is an emerging computing paradigm that overcomes the limitations of exiting Von-Neumann computing architectures such as the memory-wall bottleneck. In such paradigm, the computations are performed directly on the data stored in the memory, which highly reduces the memory-processor communications during computation. Hence, significant speedup and energy savings could be achieved especially with data-intensive applications. Associative processors (APs) were proposed in the seventies and recently were revived thanks to the high-density memories. In this tutorial brief, we overview the functionalities and recent trends of APs in addition to the implementation of each content-addressable memory with different technologies. The AP operations and runtime complexity are also summarized. We also explain and explore the possible applications that can benefit from APs. Finally, the AP limitations, challenges, and future directions are discussed.
引用
收藏
页码:2641 / 2647
页数:7
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