Geometric and electrical design verification tool for the development of GaAs digital ICs

被引:0
作者
Gupta, S
Bhattacharyya, A
机构
[1] Solid State Phys Lab, Delhi 110054, India
[2] Delhi Coll Engn, Delhi 110042, India
来源
IETE TECHNICAL REVIEW | 2001年 / 18卷 / 06期
关键词
Circuit extraction - Electrical design verification tool - Geometric design verification tool;
D O I
10.1080/02564602.2001.11416998
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A geometric and electrical design verification tool has been developed for the design verification of custom designed Gallium Arsenide (GaAs) based digital integrated circuits. To validate this tool, it is applied for the layout verification of quad D-latch and its design verification through circuit extraction. The output of circuit extraction is a file compatible to PSPICE. This extracted circuit file is simulated using PSPICE to debug errors committed during electrical design of the circuit.
引用
收藏
页码:483 / 486
页数:4
相关论文
共 4 条
[1]  
*GIG LOG INC, 1989, GAAS DIG ICS PROD MA
[2]  
GUPTA S, 1998, GEOMETRIC ELECT DESI
[3]  
HARSH SG, 1993, P 7 INT WORKSH PHYS, P204
[4]  
KANOPOLOUS N, 1989, GALLIUM ARSENIDE DIG