A dedicated DSP architecture for discrete wavelet transform

This paper presents the architecture of a DSP dedicated to discrete wavelet transform. The architecture consists in 2 microprogrammable processors whose complementarity enables to avoid any wait cycles during the algorithm execution so that the available computation power is continuously used. Thanks to this bi-processor organization, a 160000-transistor ASIC coupled to a small external SRAM implements in real time a 3-stage multiresolution transform on a CCIR 601 video signal. This chip has been realized in a 0.7 mu m double metal CMOS technology. Moreover, the DSP has a full programmability with respect to the used filters and the picture format; it also has the possibility to take into account edge effects and therefore improve image quality. The circuit can be used in the coding as well as in the decoding.