An Efficient Synchronization Circuit in Multi-Rate SDH Networks

Single-rate synchronous digital hierarchy (SDH) networks contain one master block and several slave blocks and the slaves will synchronize themselves by the master clock frequency. However, the clock frequencies of master and slaves are different in multi-rate SDH networks and hence, the slaves require a synchronization circuit to match their clock frequencies with the master clock frequency. This research presents an efficient synchronization circuit for such networks. The proposed circuit occupies smaller area than the prior circuit and requires no clock alignment for its implementation. The circuit constraints are described and the maximum clock frequencies of master and slaves are formulated. The synthetic benchmarks illustrate the circuit accuracy in various clock frequencies and show an average 51.7 % reduction on the area of synchronization circuit and an average 4.8 % reduction on the area of total system. The timing analyses of the circuit show maximum 277 and 126 MHz for master and slaves, respectively.