Variation-Aware Geometric Programming Models for the Clock Network Buffer Sizing Problem

被引:5
|
作者
Rakai, Logan [1 ]
Farshidi, Amin [1 ]
Westwick, David [1 ]
Behjat, Laleh [1 ]
机构
[1] Univ Calgary, Dept Elect & Comp Engn, Calgary, AB T2N 1N4, Canada
关键词
Clock networks; geometric programming; robust optimization; OPTIMIZATION;
D O I
10.1109/TCAD.2013.2293067
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In this paper, we present and analyze four efficient models that produce significantly improved results by optimizing conflicting power and skew objectives in the clock network buffer sizing problem. Each model is in geometric programming format and has certain advantages, such as maximum reduction in power, robustness to process variation, and striking a balance between skew and power optimization. The buffer sizing problem is formulated as a geometric programming problem to provide globally optimal solutions to the four models. We also show that a geometric programming multiobjective model can be used to optimize both power and skew without requiring any tuning from a designer. The presented self-tuning multiobjective formulation not only provides optimal solutions for buffer sizes, but also finds the tuning parameters that result in overall combined reduction in power and skew without loss of convexity. The effectiveness of the models are illustrated on several publicly available benchmarks. The models provide on average 40% to 60% improvement in power while reducing skew in several cases. We have also proposed a smart heuristic for discretization of the continuous geometric programming solution that preserves skew and power. Finally, we provide a guideline for designers to decide which one of the proposed models is the most appropriate for their needs.
引用
收藏
页码:532 / 545
页数:14
相关论文
共 11 条
  • [1] Variation-aware clock network buffer sizing using robust multi-objective optimization
    Amin Farshidi
    Logan Rakai
    Laleh Behjat
    David Westwick
    Optimization and Engineering, 2016, 17 : 473 - 500
  • [2] Variation-aware clock network buffer sizing using robust multi-objective optimization
    Farshidi, Amin
    Rakai, Logan
    Behjat, Laleh
    Westwick, David
    OPTIMIZATION AND ENGINEERING, 2016, 17 (02) : 473 - 500
  • [3] Variation-Aware Multimetric Optimization During Gate Sizing
    Ranganathan, Nagarajan
    Gupta, Upavan
    Mahalingam, Venkataraman
    ACM TRANSACTIONS ON DESIGN AUTOMATION OF ELECTRONIC SYSTEMS, 2009, 14 (04)
  • [4] Optimal transistor sizing for maximum yield in variation-aware standard cell design
    Abbas, Zia
    Olivieri, Mauro
    INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS, 2016, 44 (07) : 1400 - 1424
  • [5] Fast Variation-aware Circuit Sizing Approach for Analog Design with ML-Assisted Evolutionary Algorithm
    Song, Ling-Yen
    Kuo, Tung-Chieh
    Wang, Ming-Hung
    Liu, Chien-Nan Jimmy
    Huang, Juinn-Dar
    27TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2022, 2022, : 80 - 85
  • [6] Globally Reliable Variation-Aware Sizing of Analog Integrated Circuits via Response Surfaces and Structural Homotopy
    McConaghy, Trent
    Gielen, Georges G. E.
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2009, 28 (11) : 1627 - 1640
  • [7] Stochastic programming approaches for an energy-aware lot-sizing and sequencing problem with incentive
    Perraudat, Antoine
    Dauzere-Peres, Stephane
    Mason, Scott Jennings
    INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH, 2022, 60 (19) : 5746 - 5768
  • [8] A Memetic Algorithm based PVT Variation-aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design
    Ahmed, Mohammed Salman
    Abbas, Zia
    2019 IEEE 37TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2019), 2019, : 385 - 392
  • [9] A variable neighborhood search and mixed-integer programming models for a distributed maintenance service network scheduling problem
    Liao, Baoyu
    Lu, Shaojun
    Jiang, Tao
    Zhu, Xing
    INTERNATIONAL JOURNAL OF PRODUCTION RESEARCH, 2024, 62 (20) : 7466 - 7485
  • [10] Mixed-integer programming models and heuristic algorithms for the maximum value dynamic network flow scheduling problem
    Nixon, Tanner
    Curry, Robert M.
    Allaissem, B. Phanuel
    COMPUTERS & OPERATIONS RESEARCH, 2025, 175