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- [1] Variation-aware clock network buffer sizing using robust multi-objective optimization Optimization and Engineering, 2016, 17 : 473 - 500
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- [8] A Memetic Algorithm based PVT Variation-aware Robust Transistor Sizing Scheme for Power-Delay Optimal Digital Standard Cell Design 2019 IEEE 37TH INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD 2019), 2019, : 385 - 392