7T SRAM based Memory Cell

This research proposed a new design of memory cell of 7T SRAM using 16nm and 45nm (Arizona State University Predictive Technologies Model) PTM models. The memory cell provides larger static noise margin in hold state and a better read operation by controlling drain induces barrier lowering (DIBL) effect. With utilization of a single transistor, proposed cell provides stability of the data not only during successive read operation but also overwriting new data. Extensive simulation results using LTspice demonstrate the time delay, static noise margin and power consumption of the proposed cell.