A 4.2 nW and 18 ppm/°C Temperature Coefficient Leakage-Based Square Root Compensation (LSRC) CMOS Voltage Reference

被引：12

作者：

Huang, Chao-Jen ^{[1
]}

Lai, Yan-Jiun ^{[1
]}

Yang, Yu-Jheng Ou ^{[1
]}

Chen, Hung-Wei ^{[1
]}

Kuo, Chun-Chieh ^{[1
]}

Chen, Ke-Horng ^{[1
]}

Lin, Ying-Hsi ^{[2
]}

Lin, Shian-Ru ^{[2
]}

Tsai, Tsung-Yen ^{[2
]}

机构：

[1] Natl Chiao Tung Univ, Inst Elect & Control Engn, Hsinchu 300, Taiwan

[2] Realtek Semicond Corp, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2019年 / 66卷 / 05期

关键词：

Temperature coefficient (TC) compensation; leakage-based square root compensation (LSRC) technique; low power consumption;

D O I：

10.1109/TCSII.2019.2908284

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

State-of-the-art CMOS-based voltage reference suffer from a trade-off between power dissipation and temperature coefficient (TC) due to the limited order of compensation in an advanced process which features a low supplied voltage (1 similar to 1.2 V). The proposed voltage reference with leakage-based square root compensation (LSRC) technique bias the substrate to offset TC with ultra-low leakage current (100 similar to 300 pA). On the other hand, the architecture provides an extensible order of compensation which is independent of voltage headroom. The two LSRC branches voltage reference implemented in 40 nm CMOS process achieves a within-wafer sigma/mu of 0.204 and a TC of 18 ppm/degrees C with a power consumption of 4.2 nW.

引用

页码：728 / 732

页数：5

共 13 条

[1]

Andreou CM, 2015, IEEE INT SYMP CIRC S, P2245, DOI 10.1109/ISCAS.2015.7169129

[2] A physical alpha-power law MOSFET model [J].