A comparison design of comb decimators for sigma-delta analog-to-digital converters

被引：58

作者：

Gao, YH ^{[1
]}

Jia, LH ^{[1
]}

Isoaho, J ^{[1
]}

Tenhunen, H ^{[1
]}

机构：

[1] Royal Inst Technol, Elect Syst Design Lab, S-16440 Stockholm, Sweden

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2000年 / 22卷 / 01期

关键词：

comb decimator; non-recursive algorithm; recursive algorithm; low power; high speed; sigma-delta A/D converters;

D O I：

10.1023/A:1008372010560

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 mu m 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.

引用

页码：51 / 60

页数：10

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