Reverse engineering (RE) a register transfer level (RTL) description allows an attacker to counterfeit intellectual property (IP) as well as introduce hardware trojans. To mitigate this risk, RTL obfuscation can be employed. Most of the existing obfuscation methods are targeted at gate-level and layout-level. In this work, we propose key based RTL obfuscation scheme at an early design phase during high-level synthesis (HLS). Given a control data flow graph (CDFG), obfuscation points are identified during scheduling and obfuscation logic is inserted during the datapath generation phase. In order to keep performance overhead low, such insertion is done only on noncritical paths. We implemented the proposed obfuscation technique in an in-house HLS system and the obfuscated RTL designs were synthesized to gate-level with Synopsys Design compiler targeting 90nm CMOS technology library. Based on the experimental results on four datapath intensive benchmarks, we demonstrate that proposed approach obfuscates the design with extremely low probability of reverse engineering. For a 32-bit obfuscation key, the average area, delay, and power overheads are 2.45%, 2.65%, and 2.61% respectively, which are reasonable.
