Three-Stage Dynamic-Biased CMOS Amplifier With a Robust Optimization of the Settling Time

被引：19

作者：

Giustolisi, Gianluca ^{[1
]}

Palumbo, Gaetano ^{[1
]}

机构：

[1] Univ Catania, Dipartimento Ingn Elettr Elettron & Informat, I-95124 Catania, Italy

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS | 2015年 / 62卷 / 11期

关键词：

Feedback amplifiers; frequency compensation; settling time; three-stage amplifier; NESTED-MILLER COMPENSATION; FEEDBACK FREQUENCY-COMPENSATION; POWER MULTISTAGE AMPLIFIERS; LARGE CAPACITIVE LOAD; DESIGN METHODOLOGY; VOLTAGE BUFFER; OUTPUT STAGES; RESISTOR; OTAS;

D O I：

10.1109/TCSI.2015.2476396

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper a three-stage dynamic-biased CMOS amplifier is designed with a robust optimization of its settling-time performance. The methodology studies the stability of a third order system through the so-called "separation factors" and analyzes the settling time performance through the use of contour plots, in order to define a suitable design strategy. The approach is experimentally validated through the design of a three-stage amplifier with a new compensation network. Monte Carlo simulations as well as experimental results on an integrated prototype demonstrate the validity of the proposed method.

引用

页码：2641 / 2651

页数：11

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