Comparing the performance of a low-power high speed flip-flop in bulk and SOI technologies

被引：1

作者：

Forouzandeh, B. ^{[1
]}

Seyedi, A. S. ^{[1
]}

机构：

[1] Univ Tehran, Dept Elect & Comp Engn, Tehran, Iran

来源：

PROCEEDINGS OF THE INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2006年

关键词：

flip-flop; SOI; bulk; low power; low leakage; high speed;

D O I：

10.1109/MIXDES.2006.1706578

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the performance of Double-edge triggered Feedbacked Flip-Flop (DFFF) in SOI and Bulk technologies has been compared. DFFF power consumption is reduced by avoiding unnecessary internal node transition. The subthreshold current in this flip-flop is very low compared to the other structures. Reducing the number of transistors in the stack and increasing the number of charge path lead to less delay and thus higher operational speed compared to the other flip-flops. By using SOI technology, the power consumption and speed have been improved further compared to Bulk technology. The performance improvement is 37.10% to 45.54% for discussed flip-flops compared to Bulk technology.

引用

页码：251 / +

页数：3

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