A 117-mm(2) 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications

被引:70
作者
Jung, TS
Choi, YJ
Suh, KD
Suh, BH
Kim, JK
Lim, YH
Koh, YN
Park, JW
Lee, KJ
Park, JH
Park, KT
Kim, JR
Yi, JH
Lim, HK
机构
关键词
D O I
10.1109/JSSC.1996.542301
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
For a quantum step in further cost reduction, the multilevel cell concept has been combined with the NAND flash memory, Key requirements of mass storage, low cost, and high serial access throughput have been achieved by sacrificing fast random access performance. This paper describes a 128-Mb multilevel NAND flash memory storing 2 b per cell. Multilevel storage is achieved through tight cell threshold voltage distribution of 0.4 V and is made practical by significantly reducing program disturbance by using a local self-boosting scheme, An intelligent page buffer enables cell-by-cell and state-by-state program and inhibit operations, A read throughput of 14.0 MB/s and a program throughput of 0.5 MB/s are achieved, The device has been fabricated with 0.4-mu m CMOS technology, resulting in a 117 mm(2) die size and a 1.1 mu m(2) effective cell size.
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页码:1575 / 1583
页数:9
相关论文
共 5 条
  • [1] [Anonymous], IEEE ISSCC
  • [2] Bauer M., 1995, IEEE INT SOL STAT CI, P132
  • [3] KIM JK, 1996, S VLSI CIRCUITS DIG
  • [4] PARK JH, 1995, NVSM WORKSH DIG TECH
  • [5] TAKEUCHI K, 1995, S VLSI CIRCUITS DIG, P67