A novel low specific on-resistance double-gate LDMOS with multiple buried p-layers in the drift region based on the Silicon-On-Insulator substrate

被引：14

作者：

Chen, Yinhui ^{[1
]}

Hu, Shengdong ^{[1
,2
]}

Cheng, Kun ^{[1
]}

Jiang, YuYu ^{[1
]}

Luo, Jun ^{[2
]}

Wang, Jian'an ^{[2
]}

Tang, Fang ^{[1
]}

Zhou, Xichuan ^{[1
]}

Zhou, Jianlin ^{[1
]}

Gan, Ping ^{[1
]}

机构：

[1] Chongqing Univ, Coll Commun Engn, Chongqing 400044, Peoples R China

[2] 24 Res Inst China Elect Technol Grp Corp, Natl Lab Analogue Integrated Circuits, Chongqing 400060, Peoples R China

来源：

SUPERLATTICES AND MICROSTRUCTURES | 2016年 / 89卷

基金：

中国国家自然科学基金;

关键词：

SOI; Multiple buried p-layers; Specific on-resistance; Breakdown voltage; RESURF; PARTIAL-SOI LDMOSFET; HIGH-VOLTAGE DEVICE; BREAKDOWN VOLTAGE; ELECTRIC-FIELD; ANALYTICAL-MODEL; TRENCH;

D O I：

10.1016/j.spmi.2015.09.037

中图分类号：

O469 [凝聚态物理学];

学科分类号：

070205 ;

摘要：

A novel double-gate SOI LDMOS with multiple buried p-layers in the drift region (MBP SOI LDMOS) is proposed in this paper. MBP SOI LDMOS has two gates, the planar gate and the trench gate. The big feature of MBP LDMOS is the multiple buried p-layers with intervals in the drift region which is an arithmetic progression and decreases successively. Firstly, double gates of the structure form dual current conduction channels, leading to a low specific on-resistance (R-on,R-sp). Secondly, the multiple buried p-layers form a more significant triple RESURF effect, which not only increases the drift doping concentration but also modulates the electric field of the drift region, resulting in a low R-on,R-sp and a high breakdown voltage (BV). MBP SOI LDMOS is thus owning a reduced R-on,R-sp and an improved BV. The effects of structure parameters on the device performances are investigated. Compared with the conventional SOI LDMOS, the R-on,R-sp of MBP SOI LDMOS is reduced by 52.5% with BV increasing by 36.4% at the same 16-mu m-drift region. (C) 2015 Elsevier Ltd. All rights reserved.

引用

页码：59 / 67

页数：9

共 30 条

[1]

[Anonymous], TMA MEDICI 4 2

[2] An analytical model for breakdown voltage of surface implanted SOI RESURF LDMOS [J].

Chung, SK .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2000, 47 (05) :1006-1009

[3]

Disney DR, 2001, ISPSD'01: PROCEEDINGS OF THE 13TH INTERNATIONAL SYMPOSIUM ON POWER SEMICONDUCTOR DEVICES & ICS, P399, DOI 10.1109/ISPSD.2001.934638

[4] Significant On-Resistance Reduction of LDMOS Devices by Intermitted Trench Gates Integration [J].

Erlbacher, Tobias ;

Bauer, Anton J. ;

Frey, Lothar .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (12) :3470-3476

[5] Reduced On Resistance in LDMOS Devices by Integrating Trench Gates Into Planar Technology [J].

Erlbacher, Tobias ;

Bauer, Anton J. ;

Frey, Lothar .

IEEE ELECTRON DEVICE LETTERS, 2010, 31 (05) :464-466

[6] SOI high-voltage LDMOS with novel triple-layer top silicon based on thin BOX [J].

Hu, S. D. ;

Zhang, L. ;

Luo, J. ;

Tan, K. Z. ;

Chen, W. S. ;

Gan, P. ;

Zhou, X. C. ;

Zhu, Z. .

ELECTRONICS LETTERS, 2013, 49 (03) :223-224

[7] Design of compound buried layer SOI high voltage device with double windows [J].

Hu, S. D. ;

Luo, X. R. ;

Zhang, B. ;

Li, Z. J. .

ELECTRONICS LETTERS, 2010, 46 (01) :82-83

[8] Realizing high breakdown voltage for a novel interface charges islands structure based on partial-SOI substrate [J].

Hu, Shengdong ;

Luo, Jun ;

Tan, Kaizhou ;

Zhang, Ling ;

Li, Zhaoji ;

Zhang, Bo ;

Zhou, Jianlin ;

Gan, Ping ;

Qin, Guolin ;

Zhang, Zhengyuan .

MICROELECTRONICS RELIABILITY, 2012, 52 (04) :692-697

[9] Analytical models for the electric field distributions and breakdown voltage of Triple RESURF SOI LDMOS [J].

Hu, Xiarong ;

Zhang, Bo ;

Luo, Xiaorong ;

Li, Zhaoji .

SOLID-STATE ELECTRONICS, 2012, 69 :89-93

[10] A new high voltage SOI LDMOS with triple RESURF structure [J].

Hu Xiarong ;

Zhang Bo ;

Luo Xiaorong ;

Yao Guoliang ;

Chen Xi ;

Li Zhaoji .

JOURNAL OF SEMICONDUCTORS, 2011, 32 (07)

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