A 6-Bit 0.13 μm SiGe BiCMOS Digital Step Attenuator with Low Phase Variation for K-Band Applications

被引:1
作者
Sarfraz, Muhammad Masood [1 ,2 ,3 ]
Ullah, Farman [1 ,2 ,3 ]
Wang, Minghua [1 ,2 ]
Zhang, Haiying [1 ,2 ]
Liu, Yu [1 ,2 ]
机构
[1] Chinese Acad Sci, Beijing Key Lab Radio Frequency IC Technol Next G, Inst Microelect, Beijing 100029, Peoples R China
[2] Univ Chinese Acad Sci, Inst Microelect, 19A Yuquan Rd, Beijing 100049, Peoples R China
[3] COMSATS Univ, Wah Campus GT Rd, Wah Cantt 47040, Pakistan
来源
ELECTRONICS | 2018年 / 7卷 / 05期
基金
美国国家科学基金会;
关键词
digital attenuator; CMOS; K-band; SiGe; phase correction; RMS errors; CMOS; DISTORTION; GHZ;
D O I
10.3390/electronics7050074
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
This paper presents the design and measuring of a 6-bit SiGe BiCMOS digital step attenuator, with a maximum attenuation of 31.5 dB, and with 0.5 dB steps (64 states) that have the lowest RMS amplitude error and a low phase variation. To alleviate the large phase variation of the conventional attenuator at a higher frequency, the proposed attenuator utilizes a phase compensation circuit. The phase compensation circuit consists of a 2nd order low pass phase correction network, stacked in parallel to the switched pi/T structure of each attenuation module. An attenuator with a phase compensation network shows a root mean square (RMS) amplitude error less than 0.43 dB, and the RMS insertion phase deviation varying from 1.6 degrees to 4.2 degrees over 20-24 GHz. The measured insertion loss is 21.9 dB and the input P1dB is 14.03 dBm at 22 GHz. Our confidence regarding the obtained results stems from a comparison of simulations, carried out using Cadence Virtuoso, and physical measurements using a network analyzer (also presented). The proposed attenuator's design has a 0.13 mu m SiGe BiCMOS process, with an approximate occupied area of 1.92 x 0.4 mm(2) including chip pads.
引用
收藏
页数:11
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