Characterization of Monolithic InAlN/GaN NAND Logic Cell Supported by Circuit and Device Simulations

被引：6

作者：

Chvala, Ales ^{[1
]}

Nagy, Lukas ^{[1
]}

Marek, Juraj ^{[1
]}

Priesol, Juraj ^{[1
]}

Donoval, Daniel ^{[1
]}

Blaho, Michal ^{[2
]}

Gregusova, Dagmar ^{[2
]}

Kuzmik, Jan ^{[2
]}

Satka, Alexander ^{[1
]}

机构：

[1] Slovak Univ Technol Bratislava, Inst Elect & Photon, Bratislava 81219, Slovakia

[2] Slovak Acad Sci, Inst Elect Engn, Bratislava 84104, Slovakia

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2018年 / 65卷 / 06期

关键词：

Circuit and device simulations; InAlN/GaN high-electron mobility transistor (HEMT); monolithic integration; NAND logic cell; DUAL-GATE; INALN/(IN)GAN; HEMTS;

D O I：

10.1109/TED.2018.2828464

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this brief, the monolithic integration of enhancement (E)-mode and depletion (D)-mode InAlN/GaN high-electron mobility transistors (HEMTs) is presented. The aim of this brief is to show the results of the designed NAND logic cell, which consists of both HEMTs integrated onto a single die. Large-signalmodels of dual-gate E-mode and D-mode HEMTs are proposed and calibrated by experimental results. We present well-calibrated electrophysical models for 2-D device simulations employing mixedmode setup in Synopsys TCAD Sentaurus device. The mixed-mode approach interconnects dual-gate E-HEMT and D-HEMT to NAND logic cell circuit, which allows analysis and characterization of the device as the complex system. Good agreement between simulations and experimental results confirms the validity of the proposedmodels and simulation methodology.

引用

页码：2666 / 2669

页数：4

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