ESTIMATION AND CORRECTION OF GAIN MISMATCH AND TIMING ERROR IN TIME-INTERLEAVED ADCs BASED ON DFT

被引:14
作者
Guo, Lianping [1 ]
Tian, Shulin [1 ]
Wang, Zhigang [1 ]
机构
[1] Univ Elect Sci & Technol China, Sch Automat Engn, Chengdu 610054, Peoples R China
基金
高等学校博士学科点专项科研基金; 中国国家自然科学基金;
关键词
correction; estimation; gain mismatch; time-interleaved analog-to-digital converter; timing error; BACKGROUND CALIBRATION TECHNIQUE;
D O I
10.2478/mms-2014-0045
中图分类号
TH7 [仪器、仪表];
学科分类号
0804 ; 080401 ; 081102 ;
摘要
Time-interleaved analog-to-digital converter (ADC) architecture is crucial to increase the maximum sample rate. However, offset mismatch, gain mismatch, and timing error between time-interleaved channels degrade the performance of time-interleaved ADCs. This paper focuses on the gain mismatch and timing error. Techniques based on Discrete Fourier Transform (DFT) for estimating and correcting gain mismatch and timing error in an M-channel ADC are depicted. Numerical simulations are used to verify the proposed estimation and correction algorithm.
引用
收藏
页码:535 / 544
页数:10
相关论文
共 19 条
  • [1] TIME INTERLEAVED CONVERTER ARRAYS
    BLACK, WC
    HODGES, DA
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (06) : 1022 - 1029
  • [2] Cheng-Chung Hsu, 2007, 2007 IEEE International Solid-State Circuits Conference (IEEE Cat. No.07CH37858), P464
  • [3] An analog background calibration technique for time-interleaved analog-to-digital converters
    Dyer, KC
    Fu, DH
    Lewis, SH
    Hurst, PJ
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) : 1912 - 1919
  • [4] Elbornsson J, 2002, 2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL III, PROCEEDINGS, P129
  • [5] Elbornsson J, 2001, INT CONF ACOUST SPEE, P3913, DOI 10.1109/ICASSP.2001.940699
  • [6] A digital background calibration technique for time-interleaved analog-to-digital converters
    Fu, DH
    Dyer, KC
    Lewis, SH
    Hurst, PJ
    [J]. IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (12) : 1904 - 1911
  • [7] Gupta S. K., 2006, IEEE J SOLID-ST CIRC, V41, P2650
  • [8] Blind calibration of timing offsets for four-channel time-interleaved ADCs
    Huang, Steven
    Levy, Bernard C.
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (04) : 863 - 876
  • [9] Jamal S. M., 2002, IEEE J SOLID-ST CIRC, V37, P1618
  • [10] Calibration of sample-time error in a two-channel time-interleaved analog-to-digital converter
    Jamal, SM
    Fu, DH
    Singh, MP
    Hurst, PJ
    Lewis, SH
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2004, 51 (01) : 130 - 139