Enhanced split-architecture Δ-Σ ADC

被引：11

作者：

Lee, K. ^{[1
]}

Temes, G. C. ^{[1
]}

机构：

[1] Oregon State Univ, Kelley Engn Ctr, Dept Elect Engn & Comp Sci, Corvallis, OR 97331 USA

来源：

ELECTRONICS LETTERS | 2006年 / 42卷 / 13期

关键词：

Electric network topology - Error analysis - Spurious signal noise - System stability;

D O I：

10.1049/el:20061218

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A split Delta-Sigma ADC topology is proposed which provides enhanced noise shaping by cross-coupling the quantisation errors of the two halves of the structure. Unlike the multi-stage noise shaping architecture, the new structure is insensitive to mismatch errors and it does not reduce the stability of the loops. Simulations confirm the effectiveness of the proposed scheme.

引用

页码：737 / 739

页数：3

共 4 条

[1] A 0.9-V 12-mW 5-MSPS algorithmic ADC with 77-dB SFDR [J].

Li, JP ;

Ahn, GC ;

Chang, DY ;

Moon, UK .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (04) :960-969

[2] Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC [J].

McNeill, J ;

Coln, MCW ;

Larivee, BJ .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2005, 40 (12) :2437-2445

[3] Wideband low-distortion delta-sigma ADC topology [J].

Silva, J ;

Moon, U ;

Steensgaard, J ;

Temes, GC .

ELECTRONICS LETTERS, 2001, 37 (12) :737-738

[4]

ZHANG Z, 2005, MWSCAS 0K CINC OH US

← 1 →