A 0.4-4Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs

被引：6

作者：

Chang, KYK ^{[1
]}

Wei, J ^{[1
]}

Li, S ^{[1
]}

Li, YX ^{[1
]}

Donnelly, K ^{[1
]}

Huang, C ^{[1
]}

Sidiropoulos, S ^{[1
]}

机构：

[1] Rambus Inc, Los Altos, CA USA

来源：

2002 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2002年

关键词：

D O I：

10.1109/VLSIC.2002.1015054

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A quad high-speed transceiver cell is designed and implemented in 0.13mum CMOS technology. To achieve low jitter while maintaining low power consumption, dual on-chip regulators are used for each dual-loop PLL. The prototype chip demonstrates that the links can operate from 400Mb/s to 4Gb/s with a bit error rate < 10(-14). The quad cell consumes 390mW at 2.5Gb/s (95mW/link) under typical operating conditions with a 400mV output swing driving double terminated links.

引用

页码：88 / 91

页数：4

共 25 条

[1] A 0.4-4-Gb/s CMOS quad transceiver cell using on-chip regulated dual-loop PLLs
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Huang, C
Li, S
Donnelly, K
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Li, YX
Sidiropoulos, S
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