Cleaved-Gate Ferroelectric FET for Reliable Multi-Level Cell Storage

A novel Ferroelectric FET (FeFET) structure to enable reliable multi-level cell (MLC) storage using a cleaved gate (CG) is proposed for the first time. The CG-FeFET features a gate that is cleaved into two regions separated by an insulator. Cleaving off the gate modulates the channel conductance, and in turn, memory window (MW) and sense margin, i.e., the ratio of ID measured for low-V-T and high-V-T states [(I-D)(LVT)/(I-D)(HVT)]. The proposed CG-FeFET is investigated and optimized based on well-calibrated TCAD models. We perform an extensive design space exploration in order to evaluate: 1) the impact of the length of separation oxide (L-OX) inserted between the source side gate (G_S) and the drain side gate (G_D); 2) whether reading from G_S or G_D is better, and 3) the best placement of the insulator between the two gates comparing symmetric (L-G_S=L-G_D) vs. asymmetric (L-G_S not equal L-G_D) structures. Our investigations provide detailed guidelines for designing a CG-FeFET that exhibits 3x larger MW and 6.6x higher (I-D)(LVT)/(I-D)(HVT) compared to the baseline FeFET. Such significant improvements offered by CG-FeFET greatly increase the noise margin of the FeFET device; thus, storing four different states with an order of magnitude distinguishable sensing current. Hence, two bits can be reliably stored in CG-FeFET, opening the door for reliable MLC-FeFETs.