A 65nm 16kb SRAM with 131.5pW Leakage at 0.9V for Wireless IoT Sensor Nodes

被引：85

作者：

Gupta, Shourya ^{[1
]}

Truesdell, Daniel S. ^{[1
]}

Calhoun, Benton H. ^{[1
]}

机构：

[1] Univ Virginia, Charlottesville, VA 22903 USA

来源：

2020 IEEE SYMPOSIUM ON VLSI CIRCUITS | 2020年

关键词：

D O I：

10.1109/vlsicircuits18222.2020.9162772

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents a 16kb SRAM that achieves an ultra-low leakage of less than 132pW across its entire operational V-DD range (0.3-0.9V). It is implemented using a new robust two-port bitcell with 614aW leakage, which, to the best of the authors' knowledge, is the lowest leakage bitcell reported to date. Additionally, new peripheral techniques enable 1000x reduction in bit-line (BL) leakage, up to 69% improvement in access speed at low V-DD, and up to 63.6% reduction in peripheral circuitry area over state-of-the-art works. The SRAM achieves an array area efficiency of 67.87%, leakage power of 51.8pW to 131.5pW for V-DD at 0.3V and 0.9V, and >6.5 MHz access frequency.

引用

页数：1