Application Exploration for 3-D Integrated Circuits: TCAM, FIFO, and FFT Case Studies

被引:20
作者
Davis, W. Rhett [1 ]
Oh, Eun Chu [1 ]
Sule, Ambarish M. [1 ]
Franzon, Paul D. [1 ]
机构
[1] N Carolina State Univ, Dept Elect & Comp Engn, Raleigh, NC 27695 USA
基金
美国国家科学基金会;
关键词
Fast Fourier transform (FFT); first-in first-out (FIFO); ternary content-addressable memory (TCAM); 3-D integrated circuit (IC); HIGH-SPEED; PERFORMANCE; MEMORY; ALGORITHM; ICS;
D O I
10.1109/TVLSI.2008.2009352
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
3-D stacking and integration can provide system advantages. This paper explores application drivers and computer-aided design (CAD) for 3-D integrated circuits (ICs). Interconnect-rich applications especially benefit, sometimes up to the equivalent of two technology nodes. This paper presents physical-design case studies of ternary content-addressable memories (TCAMs), first-in first-out (FIFO) memories, and a 8192-point fast Fourier transform (FFT) processor in order to quantify the benefit of the through-silicon vias in an available 180-nm 3-D process. The TCAM shows a 23% power reduction and the FFT shows a 22% reduction in cycle-time, coupled with an 18% reduction in energy per transform.
引用
收藏
页码:496 / 506
页数:11
相关论文
共 38 条
[31]   Comparison of key performance metrics in two- and three-dimensional integrated circuits [J].
Rahman, A ;
Fan, A ;
Reif, R .
PROCEEDINGS OF THE IEEE 2000 INTERNATIONAL INTERCONNECT TECHNOLOGY CONFERENCE, 2000, :18-20
[32]  
SCHOENFLIESS K, 2006, THESIS N CAROLINA ST
[33]   Fully parallel 30-MHz, 2.5-Mb CAM [J].
Shafai, F ;
Schultz, KJ ;
Gibson, GFR ;
Bluschke, AG ;
Somppi, DE .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1998, 33 (11) :1690-1696
[34]   A current-sensed high-speed and low-power first-in-first-out memory using a wordline/bitline-swapped dual-port SRAM cell [J].
Shibata, N ;
Watanabe, M ;
Tanabe, Y .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2002, 37 (06) :735-750
[35]  
TARJAN D, 2006, CACTI 4 0
[36]   A TERNARY CONTENT ADDRESSABLE SEARCH ENGINE [J].
WADE, JP ;
SODINI, CG .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1989, 24 (04) :1003-1013
[37]   Double-edge-triggered address pointer for low-power high-speed FIFO memories [J].
Wang, H ;
Liu, PC .
ELECTRONICS LETTERS, 1997, 33 (05) :387-389
[38]   Implementing a 2-Gbs 1024-bit 1/2-rate Low-Density Parity-Check Code Decoder in Three-Dimensional Integrated Circuits [J].
Zhou, Lili ;
Wakayama, Cherry ;
Panda, Robin ;
Jangkrajarng, Nuttorn ;
Hu, Bo ;
Shi, C. -J. Richard .
2007 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, VOLS, 1 AND 2, 2007, :194-201