Sign Detection and Number Comparison on RNS 3-Moduli Sets {2n-1, 2n+x, 2n+1}

Number comparison, sign identification and overflow detection are important operations, especially for digital signal processing, but hard to perform using the residue number system (RNS). In this paper, a new method is proposed for sign identification and number comparison based on an optimized version of the mixed radix conversion for the augmented 3-moduli sets . Notably, most of the computations are directly performed on the moduli channels, thus allowing to easily adapt this new method to any RNS processor. Accordingly, this paper proposes an efficient unified very large scale integration architecture based on the presented methodology, which can be used not only to design application specific integrated circuits (ASICs) but also to configure field-programmable gate arrays (FPGAs). The implementation results that were obtained using CMOS technologies show that the proposed architecture provided comparators that are more efficient than the related state of the art, by considering as a figure of merit the area time product. More specifically, the considered ASIC and FPGA implementations provide relative improvements in the efficiency of up to 57 and , respectively. The experimental assessment also shows that the power consumption of the proposed circuits is significantly lower than the related state of the art, with relative reductions of up to .