An ultra-low-power neural signal acquisition analog front-end IC

被引:18
作者
Tran, Luat [1 ]
Cha, Hyouk-Kyu [1 ]
机构
[1] Seoul Natl Univ Sci & Technol, Dept Elect & Informat Engn, 232 Gongneung Ro, Seoul 01811, South Korea
来源
MICROELECTRONICS JOURNAL | 2021年 / 107卷 / 107期
基金
新加坡国家研究基金会;
关键词
Analog front-end; Neural recording amplifier; Programmable gain amplifier; Low-noise; Inverter-stacking; AMPLIFIER;
D O I
10.1016/j.mejo.2020.104950
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A four-channel, power-efficient, low-noise neural recording analog front-end (AFE) integrated circuit (IC) comprised of a low-noise amplifier (LNA), a programmable gain amplifier (PGA), and buffers is presented. The proposed AC-coupled capacitive-feedback LNA utilizes the inverter-stacking technique for the core operational transconductance amplifier which achieves four-time reduction in noise at minimal power consumption. The proposed PGA provides additional gain with tunable filtering function where the high-pass cut-off and low-pass cut-off frequencies can be controlled to acquire action potential and local field potential signals either simultaneously or separately. The overall AFE IC has a programmable gain range from 45 dB to 63 dB and achieves integrated input-referred noise of 3.16 mu V-RMS within the 10 kHz bandwidth, leading to a noise efficiency factor of 2.04 and power efficiency factor of 4.16. The AFE IC is implemented using 180 nm CMOS process and consumes 2.82 mu W per channel powered from the 1-V supply voltage.
引用
收藏
页数:8
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