Threshold voltage model of junctionless cylindrical surrounding gate MOSFETs including fringing field effects

被引:20
作者
Gupta, Santosh Kumar [1 ]
机构
[1] Motilal Nehru Natl Inst Technol, Dept Elect & Commun Engn, Allahabad 211004, Uttar Pradesh, India
关键词
Junctionless (JL) MOSFET; Fringing fields; Threshold voltage; Cylindrical surrounding gate (CSG); Evanescent mode analysis (EMA); CAPACITANCE;
D O I
10.1016/j.spmi.2015.09.001
中图分类号
O469 [凝聚态物理学];
学科分类号
070205 ;
摘要
2D Analytical model of the body center potential (BCP) in short channel junctionless Cylindrical Surrounding Gate (JLCSG) MOSFETs is developed using evanescent mode analysis (EMA). This model also incorporates the gate bias dependent inner and outer fringing capacitances due to the gate-source/drain fringing fields. The developed model provides results in good agreement with simulated results for variations of different physical parameters of JLCSG MOSFET viz, gate length, channel radius, doping concentration, and oxide thickness. Using the BCP, an analytical model for the threshold voltage has been derived and validated against results obtained from 3D device simulator. (C) 2015 Elsevier Ltd. All rights reserved.
引用
收藏
页码:188 / 197
页数:10
相关论文
共 20 条
  • [1] Two-dimensional analytical threshold voltage roll-off and subthreshold swing models for undoped cylindrical gate all around MOSFET
    Abd-Elhamid, Hamdy
    Iniguez, Benjamin
    Jimenez, David
    Roig, Jaume
    Pallares, Josep
    Marsal, Lluis F.
    [J]. SOLID-STATE ELECTRONICS, 2006, 50 (05) : 805 - 812
  • [2] Charge-based continuous model for long-channel Symmetric Double-Gate Junctionless Transistors
    Cerdeira, A.
    Estrada, M.
    Iniguez, B.
    Trevisoli, R. D.
    Doria, R. T.
    de Souza, M.
    Pavanello, M. A.
    [J]. SOLID-STATE ELECTRONICS, 2013, 85 : 59 - 63
  • [3] Chiang TK, 2012, IEEE C ELEC DEVICES
  • [4] Colinge JP, 2010, NAT NANOTECHNOL, V5, P225, DOI [10.1038/nnano.2010.15, 10.1038/NNANO.2010.15]
  • [5] Simple Analytical Bulk Current Model for Long-Channel Double-Gate Junctionless Transistors
    Duarte, Juan P.
    Choi, Sung-Jin
    Moon, Dong-Il
    Choi, Yang-Kyu
    [J]. IEEE ELECTRON DEVICE LETTERS, 2011, 32 (06) : 704 - 706
  • [6] A junctionless tunnel field effect transistor with low subthreshold slope
    Ghosh, Bahniman
    Bal, Punyasloka
    Mondal, Partha
    [J]. JOURNAL OF COMPUTATIONAL ELECTRONICS, 2013, 12 (03) : 428 - 436
  • [7] Physical Model of the Junctionless UTB SOI-FET
    Gnani, Elena
    Gnudi, Antonio
    Reggiani, Susanna
    Baccarani, Giorgio
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2012, 59 (04) : 941 - 948
  • [8] Theory of the Junctionless Nanowire FET
    Gnani, Elena
    Gnudi, Antonio
    Reggiani, Susanna
    Baccarani, Giorgio
    [J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2011, 58 (09) : 2903 - 2910
  • [9] Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects
    Gupta, Santosh K.
    Baishya, Srimanta
    [J]. JOURNAL OF SEMICONDUCTORS, 2013, 34 (07)
  • [10] Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region
    Holtij, Thomas
    Schwarz, Mike
    Kloes, Alexander
    Iniguez, Benjamin
    [J]. SOLID-STATE ELECTRONICS, 2013, 90 : 107 - 115