System-on-package (SOP) technology, characterization and applications

被引：18

作者：

Knickerbocker, J. U. ^{[2
]}

Andry, P. S. ^{[2
]}

Buchwalter, L. P. ^{[2
]}

Colgan, E. G. ^{[2
]}

Cotte, J. ^{[2
]}

Gan, H. ^{[1
]}

Horton, R. R. ^{[2
]}

Sri-Jayantha, S. M. ^{[2
]}

Magerlein, J. H. ^{[2
]}

Manzer, D. ^{[2
]}

McVicker, G. ^{[2
]}

Patel, C. S. ^{[2
]}

Polastre, R. J. ^{[2
]}

Sprogis, E. S. ^{[1
]}

Tsang, C. K. ^{[2
]}

Webb, B. C. ^{[2
]}

Wright, S. L. ^{[2
]}

机构：

[1] IBM Syst & Technol Grp, 2070 Route 52, Hopewell Junct, Fishkill, NY 12533 USA

[2] IBM Corp, TJ Watson Res Ctr, Yorktown Hts, NY 10598 USA

来源：

56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS | 2006年

关键词：

D O I：

10.1109/ECTC.2006.1645680

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

A silicon-based system-on-package (SOP) is described. Novel capabilities of SOP are expected to enable lower cost, more efficient and higher performance electronic systems. Newly developed technology elements include: electrical silicon through-vias, fine-pitch, high bandwidth wiring, fine pitch solder interconnection, fine pitch known-good-die, and advanced microchannel cooling. Applications may range from miniaturized consumer products such as integrated function cell phones to high performance computers. SOP technology and related chip stacking challenges have been investigated and robust technology options are reported. Silicon through-vias can be fabricated using copper, tungsten, composite or alternate conductors. Via design and structure are discussed for vias in thin silicon packages mounted on a supporting substrate as well as thick silicon package that can be handled without a supporting substrate. Fine-pitch, high bandwidth wiring has been fabricated, characterized and shows greatest bandwidth for shorter interconnection distances. Fine pitch area array solder interconnections have been fabricated and characterized electrically, mechanically and with accelerated reliability testing. These fine pitch interconnections can enable the high bandwidth wiring for chip-to-chip interconnection. Integrated decoupling capacitors have been fabricated using parallel plate and trench technology. The integrated decoupling capacitors can provide under-chip, low inductance bypassing to minimize noise from simultaneous switching noise. New fine pitch, area array test technology provides a path to wafer level test for known-good-die, functional test, and bum-in for the fine pitch chip I/O. Advanced microchannel cooling can be leveraged to support high power, close proximity chips and chip stacks for cooling > 300 W/cm(2). This IBM Research paper describes the design, technical challenges and progress for next generation SOP technology, chip stacking, characterization, and potential new applications.

引用

页码：415 / +

页数：3

共 17 条

[1]

ANDRY P, 2006, P 56 EL COMP TECHN C

[2]

ANDRY P, 2005, IBM INTERNAL STRUCTU

[3]

COLGAN EG, IEEE SEMITHERM 2005, P1

[4]

DEUTSCH A, IEEE T ELECTROMAGNET, V43, P446

[5]

FAROOQ MG, Patent No. 6791133

[6]

GAN H, 2006, P 56 EL COMP TECHN C

[7]

Guarini KW, 2002, INTERNATIONAL ELECTRON DEVICES 2002 MEETING, TECHNICAL DIGEST, P943, DOI 10.1109/IEDM.2002.1175992

[8]

HUNTER M, P 54 ECTC 2004

[9]

Knickerbocker JU, 2005, IEEE CUST INTEGR CIR, P659

[10] Development of next-generation system-on-package (SOP) technology based on silicon carriers with fine-pitch chip interconnection [J].

Knickerbocker, JU ;

Andry, PS ;

Buchwalter, LP ;

Deutsch, A ;

Horton, RR ;

Jenkins, KA ;

Kwark, YH ;

McVicker, G ;

Patel, CS ;

Polastre, RJ ;

Schuster, C ;

Sharma, A ;

Sri-Jayantha, SM ;

Surovic, CW ;

Tsang, CK ;

Webb, BC ;

Wright, SL ;

McKnight, SR ;

Sprogis, EJ ;

Dang, B .

IBM JOURNAL OF RESEARCH AND DEVELOPMENT, 2005, 49 (4-5) :725-753

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