An edge-based dual adaptive decision feedback equalizer for Gbps serial links

被引：1
|
作者：
Al-Taee, Alaa R. [1 ,3 ]
Dolan, Matthew [2 ]
Yuan, Fei [1 ]
机构：
[1] Ryerson Univ, Dept Elect & Comp Engn, Toronto, ON, Canada
[2] Ryerson Univ, Dept Elect & Comp Engn, Microsyst Res Lab, Toronto, ON, Canada
[3] Australian Coll Kuwait, Dept Elect, Kuwait, Kuwait
来源：
ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2017年 / 90卷 / 02期
关键词：
Serial links; Decision feedback equalizers (DFEs); Edge DFE; CMOS circuits and systems; EYE-OPENING MONITOR; RECEIVER; CMOS; CDR;
D O I：
10.1007/s10470-016-0804-3
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents an adaptive edge-DFE for 2PAM Gbps serial links. The optimal tap coefficients of the DFE are obtained by minimizing the jitter of received data. Reference voltage for generating DFE error signal is also obtained iteratively using an edge-DFE like algorithm. Issues critical to the proposed adaptive edge-DFE are examined in detail. The effectiveness of the proposed adaptive edge-DFE has been validated using a 5 Gbps serial link designed in a 65 nm 1.2 V CMOS technology. The effect of PVT (process, voltage, and temperature) variations on the performance of the proposed DFE has also been investigated. Simulation results demonstrate that the DFE is capable of opening completely closed data eyes when the DFE is absent. Equalized data have 55 % vertical-opening and 86.5 % horizontal eye-opening with 25 ns adaption time.
引用
收藏
页码：399 / 409
页数：11
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