Design and Analysis of System on a Chip Encoder for JPEG2000

被引:19
作者
Dyer, Mike [1 ]
Nooshabadi, Saeid [2 ]
Taubman, David [3 ]
机构
[1] Provis Commun, Bristol BS2 8RR, Avon, England
[2] Gwangju Inst Sci & Technol, Dept Informat & Commun, Kwangju 500712, South Korea
[3] Univ New S Wales, Sydney, NSW 2052, Australia
关键词
Arithmetic coder; block coder; digital architectures; embedded block coder with optimal truncation (EBCOT); JPEG2000; MQ coder; software/hardware codesign; system on a chip; ARCHITECTURE;
D O I
10.1109/TCSVT.2008.2009245
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Much work has been performed on optimizing the throughput of the block coding system within JPEG2000. However, the question remains as to whether providing parallel simple block coders provides a cheaper method of increasing throughput than complicated optimized block coders. We present the analysis and results for a system on a chip (SoC) software/hardware codesign platform, for parallel coding in JPEG2000 compression standard. We design both a simple and a high performance, optimized peripheral encoder as a hardware accelerator for the JPEG2000 SoC encoding system. The system is implemented on an Altera NIOS II processor with flexible integrated peripheral. We show that there are optimum numbers of parallel block coders and scheduling granularity per row of codeblocks, and that parallel optimized encoders outperform parallel simple encoders. We also demonstrate that the block coding system becomes work starved rather than memory blocked when many parallel coders are present, indicating a discrete wavelet transform bottleneck.
引用
收藏
页码:215 / 225
页数:11
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