Series RLC Resonant Circuit Used as Frequency Multiplier

被引:4
作者
Lara-Reyes, Josue [1 ]
Ponce-Silva, Mario [1 ]
Hernandez-Gonzalez, Leobardo [2 ]
DeLeon-Aldaco, Susana E. [1 ]
Cortes-Garcia, Claudia [1 ]
Ramirez-Hernandez, Jazmin [2 ]
机构
[1] Tecnol Nacl Mexico CENIDET, Cuernavaca 62490, Morelos, Mexico
[2] Inst Politecn Nacl, ESIME Culhuacan, Mexico City 07738, DF, Mexico
关键词
resonant circuits; frequency multiplier; transient state design; analog frequency multiplier; underdamped response; POWER; CONVERTER; INVERTER; DEGRADATION; DESIGN; NBTI;
D O I
10.3390/en15249334
中图分类号
TE [石油、天然气工业]; TK [能源与动力工程];
学科分类号
0807 ; 0820 ;
摘要
Currently, the design of resonant power converters has only been developed while operating in the steady state, while the design operating in the transient stage has not been considered nor reported. This paper is interested in testing the performance of the resonant circuits operating in the transient stage and finding applications where benefits can be obtained from this form of operation. One application in which it is possible to obtain benefits from designing resonant circuits in the transient state is in the area of frequency multiplication. Usually, to achieve frequency multiplication, it is necessary to resort to complex methods and special devices that increase the complexity of the design and the total cost of the circuit. This paper evaluates the performance of a series RLC resonant circuit operating in the transient stage and with an underdamped response acting as a frequency multiplier, where the oscillation frequency of the current in the resonant tank is "n" number of times the switching frequency of the square voltage source at the input with a duty cycle of D = 50%. To validate the analysis, a circuit was designed to deliver an output power of 30 watts to a resistive load, where the switching frequency of the square voltage source at the input was 500 kHz. Since a multiplier value "n" equal to fifteen was chosen, the current in the resonant tank reached an oscillation frequency of 7.5 MHz. The design methodology was validated by simulations in SPICE, complying with the established design parameters.
引用
收藏
页数:18
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