Low Jitter Circuits in Digital System using Phase Locked Loop

It is important to eliminate noise at the early stages of communication systems. The Phase-Locked Loop (PLL) is designed to simplify different tasks such as clock recovery, data retiming, frequency translation and clock smoothing applications. The output signal from a given PLL suffers from an associated jitter especially at high bit rate resulting in bit errors at the receiver side and may cause malfunctioning for the all network if this error exceeds a certain threshold level. Lots of research work has been done towards analyzing, modeling and overcoming the problem of jitter associated with clock recovery circuits. One of the most recent approaches is to use a de-jitter circuit that uses a PLL clock recovery circuit by using another PLL with quartz stabilized (Voltage Controlled Crystal Oscillator) VCXO which gives superior stability and jitter performance. In this paper, the problem of jitter in clock recovery circuits will be studied and analyzed. The main objective is to develop an improved de-jitter circuit that may add some features to the already existing VCXO technique.