COMPARATOR DESIGN FOR LOW POWER HIGH SPEED FLASH ADC-A REVIEW

被引：0
|
作者：
Chacko, Litty [1 ]
Varghese, George Tom [1 ]
机构：
[1] St Josephs Coll Engn & Technol, Elect & Commun Engn, Palai, Kerala, India
来源：
PROCEEDINGS OF THE 2019 3RD INTERNATIONAL CONFERENCE ON COMPUTING METHODOLOGIES AND COMMUNICATION (ICCMC 2019) | 2019年
关键词：
Flash ADC; Comparator; Clock gating; Power dissipation;
D O I：
10.1109/iccmc.2019.8819762
中图分类号：
TP301 [理论、方法];
学科分类号：
081202 ;
摘要：
Analog to Digital Converters play a significant role in the semiconductor industry. Due to the advancements in the field of wireless technology, ADCs are widely used to convert the analog signals to the digital format. Different types of ADCs are available and among these, flash ADCs are the fastest and so they are used for large bandwidth applications. Resistor ladder, comparator and encoder are the building blocks of flash ADC. Comparator section has a direct impact on the overall performance of ADC. So this paper compares various comparator topologies and finally a suitable design for flash ADC is suggested.
引用
收藏
页码：869 / 872
页数：4
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