Barrier Synchronization for CELL Multi-Processor Architecture

被引：2

作者：

Bai, Shuwei ^{[1
]}

Zhou, Qingguo ^{[1
]}

Zhou, Rui ^{[1
]}

Li, Lian ^{[1
]}

机构：

[1] Lanzhou Univ, SISE, Distributed & Embedded Syst Lab, Lanzhou 730000, Peoples R China

来源：

2008 FIRST IEEE INTERNATIONAL CONFERENCE ON UBI-MEDIA COMPUTING AND WORKSHOPS, PROCEEDINGS | 2008年

关键词：

CELL; barrier synchronization; mailbox; signal notification register;

D O I：

10.1109/UMEDIA.2008.4570882

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Cell microprocessor is a new multi-processors system, which has been used for sonsumer electronics, multimedia decoding/encoding, compress or uncompressing area[3]. One important development technology for multi-processor system is barrier synchronization, which can improve the system performance if the appreciated barrier is adopted Based three different communication mechanisms (mailbox, dma, and signal notification register) offered by CELL system, we implement three kinds of barrier implementation tools on the CELL multi-processor system. In the paper, we will show the implementation of barrier synchronization tools and compare the barriers from three aspects: spu size, performance, and synchronization information capacity.

引用

页码：155 / 158

页数：4