Optimization of Ferroelectric Phase in Poly(vinylidene fluoride co-hexafluoropropylene under Different Annealing Conditions

Field-effect transistors (FETs) arc considered promising devices for future development owing to their application in large-area electronics. In this research, we focus on the fabrication and optimization of the ferroelectric phase of an FET by utilizing poly(vinylidene fluoride co-hexafluoropropylene) [P(VDF-co-HFP)] as a gate insulator and pentacene as an organic semiconductor under different annealing conditions. The FET was fabricated by mixing P(VDF-co-HFP) with a preformulated concentration of methyl ethyl ketone and by spin coating this mixture onto the gate electrode. The obtained gate insulator was annealed for 1 h at temperatures ranging from 110 to 170 degrees C in increments of 20 degrees C for an analysis of the underlying effect of temperature on the properties of P(VDF-co-HFP). The results show that the FET fabricated at the optimized temperature of 150 degrees C exhibits significantly improved hysteresis loop and on/off ratio. This investigation led to the development of a simple method of designing and preparing an FET with excellent electrical characteristics.