Evaluation of ASML ATHENA alignment system on intel front-end processes

An evaluation of the ASML ATHENA alignment system was performed using marks placed in the scribeline of an Intel test chip used for 130 nm node processing. Exposures were performed using two ASML scanners at IMEC at the isolation, gate, contact and first metal layers, with extreme process splits performed at Intel at critical steps in between. The splits were arranged as factorials in order to evaluate the process sensitivity of the alignment system. The modeled overlay terms with the largest sensitivities are discussed. In addition, data taken by the scanners on various mark/recipe combinations is analyzed to provide insight into overlay optimization and potential alignment system limitations.