Data-retention flip-flops for power-down applications

被引：0

作者：

Mahmoodi-Melmand, H ^{[1
]}

Roy, K ^{[1
]}

机构：

[1] Purdue Univ, Sch Elect & Comp Engn, W Lafayette, IN 47907 USA

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A novel technique for retaining data in flip-flops in power-down applications is presented. In flip-flops data is stored in cross-coupled inverters. Cross-coupled inverters can hold their states in the power down mode, if their inputs are properly gated. Based on this fact, simple clock and data gating circuitries are employed in flip-flops to retain their data in the power-down mode without using any extra data-preserving latches. In a predictive 70nm technology node, a transmission-gate flip-flop based on the proposed data-retention scheme exhibits 18X reduction in standby leakage compared to a conventional transmission-gate flip-flop. The proposed data-retention scheme also exhibits 40% area reduction compared to the conventional balloon scheme. A 16-bit shift-register using data-retention flip-flops has been successfully fabricated and tested in a 0.25mum CMOS process.

引用

页码：677 / 680

页数：4

共 9 条

[1] A low power data holding circuit with an intermittent power supply scheme for sub-1V MT-CMOS LSIs [J].

Akamatsu, H ;

Iwata, T ;

Yamamoto, H ;

Hirata, T ;

Yamauchi, H ;

Kotani, H ;

Matsuzawa, A .

1996 SYMPOSIUM ON VLSI CIRCUITS - DIGEST OF TECHNICAL PAPERS, 1996, :14-15

[2]

KAO J, 2001, EUR SOL STAT CIRC C

[3] Conditional-capture flip-flop for statistical power reduction [J].

Kong, BS ;

Kim, SS ;

Jun, YH .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (08) :1263-1271

[4]

Kumagai K., 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), P44, DOI 10.1109/VLSIC.1998.687998

[5]

Makino H., 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215), P42, DOI 10.1109/VLSIC.1998.687997

[6]

PARTOVI H, 1996, IEEE INT SOL STAT CI, P138

[7] Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits [J].

Roy, K ;

Mukhopadhyay, S ;

Mahmoodi-Meimand, H .

PROCEEDINGS OF THE IEEE, 2003, 91 (02) :305-327

[8] A 1-V high-speed MTCMOS circuit scheme for power-down application circuits [J].

Shigematsu, S ;

Mutoh, S ;

Matsuya, Y ;

Tanabe, Y ;

Yamada, J .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1997, 32 (06) :861-869

[9]

BERKELEY PREDICITIVE

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