A 14,5 GHz-0,35 μm frequency divider for dual-modulus prescaler

被引：8

作者：

Tournier, E ^{[1
]}

Sié, M ^{[1
]}

Graffeuil, J ^{[1
]}

机构：

[1] CNRS, LAAS, F-31077 Toulouse 04, France

来源：

2002 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS | 2002年

关键词：

D O I：

10.1109/RFIC.2002.1012037

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper reports on structures of frequency divider to be used in the first stage of a dual modulus prescaler. A divider by 2, the prescaler elementary cell, has been designed and characterized. A 4/5 divider is presented as a natural extension of the divider by 2. A first realization has been characterized. We show that an asynchronous structure can overcome the synchronous structure frequency limitations.

引用

页码：227 / 230

页数：4

共 6 条

[1] A 1.2 GHz CMOS dual-modulus prescaler using new dynamic D-type flip-flops [J].