Selective low temperature microcap packaging technique through flip chip and wafer level alignment

被引:13
作者
Pan, CT [1 ]
机构
[1] Natl Sun Yat Sen Univ, Dept Mech & Electro Mech Engn, Kaohsiung 804, Taiwan
[2] Natl Sun Yat Sen Univ, Ctr Nanosci & Nanotechnol, Kaohsiung 804, Taiwan
关键词
D O I
10.1088/0960-1317/14/4/012
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
In this study, a new technique of selective microcap bonding, for packaging 3-D MEMS (Micro Electro Mechanical Systems) devices is presented. Microcap bonding on a selected area of the host wafer was successfully demonstrated through flip chip and wafer level alignment. A passivation treatment was developed to separate the microcap from the carrier wafer. A thick metal nickel (Ni) microcap was fabricated by an electroplating process. Its stiffness is superior to that of thin film poly-silicon made by the surface micromachining technique. For the selective microcap packaging process, photo definable materials served as the intermediate adhesive layer between the host wafer and the metal microcap on the carrier wafer. Several types of photo definable material used as the adhesive layer were tested and characterized for bonding strength. The experimental result shows that excellent bonding strength at low bonding temperature can be achieved.
引用
收藏
页码:522 / 529
页数:8
相关论文
共 50 条
  • [31] Low temperature bonding process for wafer-level MEMS packaging
    Wei, J
    Wong, CK
    Lee, LC
    2004 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS, 2004, : A19 - A26
  • [32] Backend processing for wafer level chip scale packaging
    Hunt, JR
    IEEE/CPMT/SEMI(R) 28TH INTERNATIONAL ELECTRONICS MANUFACTURING TECHNOLOGY SYMPOSIUM, 2003, : 187 - 193
  • [33] Development of low-temperature wafer level vacuum packaging for microsensors
    Huang, WF
    Shie, JS
    Lee, C
    Gong, SC
    Peng, CJ
    DESIGN, CHARACTERIZATION, AND PACKAGING FOR MEMS AND MICROELECTRONICS, 1999, 3893 : 478 - 485
  • [34] Low temperature, wafer level Au-In bonding for ISM packaging
    Wang, Qian
    Jung, Kyudong
    Choi, Minseog
    Kim, Woonbae
    Ham, Sukjin
    Jeong, Byunggil
    Moon, Changyoul
    ICEPT: 2006 7TH INTERNATIONAL CONFERENCE ON ELECTRONICS PACKAGING TECHNOLOGY, PROCEEDINGS, 2006, : 498 - +
  • [35] Low Temperature Dielectric Material for Embedded Micro Wafer Level Packaging
    Su, Nandar
    Rao, Vempati Srinivas
    Wee, Ho Soon
    Sharma, Gaurav
    Ying, Lim Ying
    Kumar, Aditya
    Damaruganath, Pinjala
    2009 11TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC 2009), 2009, : 197 - 201
  • [36] Comparison of Package-on-Package Technologies Utilizing Flip Chip and Fan-Out Wafer Level Packaging
    Lujan, Amy P.
    2018 IEEE 68TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE (ECTC 2018), 2018, : 2089 - 2094
  • [37] D-Band Flip-Chip Packaging with Wafer-Level Cu-pillar Bumps
    Cao, Zhibo
    Stocchi, Matteo
    Wipf, Christian
    Lehmann, Jens
    Li, Lei
    Wipf, Selin Tolunay
    Wietstruck, Matthias
    Carta, Corrado
    Kaynak, Mehmet
    2023 IEEE 32ND CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS, EPEPS, 2023,
  • [38] Wafer-Level Flip Chip enabled with solid underfill
    Gilleo, K
    Blumel, D
    2000 HD INTERNATIONAL CONFERENCE ON HIGH-DENSITY INTERCONNECT AND SYSTEMS PACKAGING, 2000, 4217 : 128 - 133
  • [39] Solder wetting in a wafer-level flip chip assembly
    Lu, J
    Busch, SC
    Baldwin, DF
    51ST ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2001, : 372 - 377
  • [40] Novel materials and processes for wafer pre-apply flip chip and chip scale packaging
    Tong, Q
    Xiao, A
    Dutt, G
    Hong, S
    52ND ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, 2002 PROCEEDINGS, 2002, : 411 - 416